What are the IA-32 processor targeting options in the 11.x compilers?

Processor-specific options of the form /arch:x on Windows* ( -m on Linux* or Mac OS* X) generate specialized code for processors specified by . The resulting executables from these processor-specific options can be run on the specified or later Intel® and compatible, non-Intel® processors that support the instruction set. The executable may incorporate optimizations specific to those processors and use a specific version of the Streaming SIMD Extensions (SSE) instruction set; on older processors without support for the corresponding instruction set, and illegal instruction or similar error may occur.


Processor-specific options of the form /Qx on Windows*( -x on Linux* or Mac OS* X) generate specialized code for processors specified by . The resulting executables from these processor-specific options can only be run on the specified or later Intel® processors, as they incorporate optimizations specific to those processors and use a specific version of the Streaming SIMD Extensions (SSE) instruction set. This switch enables some optimizations not enabled with the correpsonding switchws /arch:x or -m. A run-time check is inserted in the resulting executable that will halt the application if run on an incompatible processor. This is intended to help you quickly find out that the program was not intended for the processor it is running on and potentially avoids an illegal instruction error.


Processor-dispatch options of the form /Qax on Windows* ( -ax on Linux* or Mac OS* X) allows the generation of multiple code paths for Intel® processors. Processor dispatch technology performs a check at execution time to determine which processor the application is running on and use the best code path that is compatible with that processor. Compatible, non-Intel processors will take the default code path. The switches described in 1. and 2. above can be used to modify the default code path.


Where the value for can be:
AVX
May generate Intel® AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE instructions for Intel® processors. Optimizes for a future Intel processor.
SSE4.2
May generate Intel® SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE instructions for Intel® processors. Optimizes for the Intel® Core™ i7 processor family and the Intel® Xeon® 55XX series.
SSE4.1
May generate Intel® SSE4.1,SSSE3, SSE3, SSE2, and SSE instructions for Intel® processors. Optimizes for the 45nm Hi-k next generation Intel® Core™ microarchitecture.
SSSE3
May generate Intel® SSSE3, SSE3, SSE2, and SSE in structions for Intel® processors. Optimizes for Intel® Core™ microarchitecture. -xssse3 is the default for the Intel® 64 compiler on Mac OS* X.
SSE3
May generate Intel® SSE3, SSE2, and SSE instructions. Optimizes for the enhanced Pentium M processor microarchitecture and Intel® Netburst microarchitecture. -xsse3 is the default for the IA-32 compiler on Mac OS* X.
SSE3_ATOM
May generate Intel® SSE3, SSE2, SSE and MOVBE instructions for Intel processors. Optimizes for the Intel® Atom™ processor and Intel® Centrino® Atom™ Processor Technology.
SSE2
May generate Intel® SSE2 and SSE instructions. Optimizes for the Intel® Netburst microarchitecture. /arch:SSE2 is the default on Windows* and -msse2 is the default on Linux*.
IA32
Generates generic IA32 compatible code. Can only be used with the /arch: or -m switches.